Importance

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Abstract

A clock divider circuit including a clock input, a clock selection input, a divider stage and a toggle stage is provided. The clock divider circuit provides an output clock based on a clock input received at the clock input. The clock selection input is coupled to the divider stage, and the divider stage is coupled to the toggle stage. A clock divide setting is updated at the clock selection input synchronously to an operation of the divider stage. In one implementation, for example, the clock divider setting is updated seamlessly. A method of transitioning an output clock signal is also provided. The method includes receiving an input clock signal and a first clock divide setting; providing an output clock signal having a first output clock frequency by dividing the input clock signal based upon the first clock divide setting utilizing a divider stage of a clock divider circuit; providing an updated second clock divide setting synchronously to an operation of the divider stage; and transitioning the output clock signal to a second output clock frequency based upon the updated second clock divide setting. A power management system is also provided.

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First Claim