DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY

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United States of America Patent

APP PUB NO 20110133795A1
SERIAL NO

12790242

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Abstract

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There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRO-MECHANICS CO LTDGYEONGGI DO SOUTH KOREA GYEONGGI-DO
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYDAEJEON 34141

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHO, Seong Hwan Daejeon, KR 25 99
KIM, Gyu Suck Seoul, KR 23 177
SON, Woo Kon Daegu, KR 1 5

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