Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer in Mission Mode

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United States of America Patent

APP PUB NO 20110150060A1
SERIAL NO

12645612

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Abstract

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Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1's and 0's) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link.

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Patent Owner(s)

Patent OwnerAddress
SUN MICROSYSTEMS INC4150 NETWORK CIRCLE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Del, Alamo Agustin San Diego, US 2 19
Doblar, Drew G San Jose, US 55 1123
Huang, Dawei San Diego, US 48 268
Song, Deqiang San Diego, US 17 48

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