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Abstract

Disclosed is a method of manufacturing a CMOS image sensor, capable of forming silicide in a logic region and facilitating ion implantation into a pixel region while keeping a hard mask layer in a thin thickness without performing a process for removing the hard mask layer. The critical dimension is easily controlled when forming a gate pattern and the uniformity in the critical dimension of a gate photoresist pattern is improved. The method includes the steps of forming a gate conductive layer on a substrate on which a pixel region and a logic region are defined; forming a hard mask pattern on the gate conductive layer in such a manner that a thickness of the hard mask pattern in the pixel region is thicker than a thickness of the hard mask pattern in the logic region; forming a gate pattern in the pixel region and the logic region by etching the gate conductive layer using the hard mask pattern as an etching barrier; removing the hard mask pattern remaining in the logic region; and forming silicide in the logic region.

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First Claim