Dual Interconnection in Stacked Memory and Controller Module

United States of America Patent

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Mar 18, 2011
filing date
Apr 28, 2009

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Abandoned

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Abstract

A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

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Patent Owner(s)

Patent Owner	Address
WAFER-LEVEL PACKAGING PORTFOLIO LLC	CUPERTINO CA

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H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Marcoux, Phil P	Mountain View, US	12	1152

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Dual Interconnection in Stacked Memory and Controller Module

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United States of America Patent

13051917

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