Processor circuit with shared memory and buffer system
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United States of America Patent
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Jun 23, 2015
Grant Date -
Jul 28, 2011
app pub date -
Jul 23, 2009
filing date -
Jul 25, 2008
priority date (Note) -
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Abstract
The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.
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