Fault-and Variation-Tolerant Energy - and Area-Efficient Links for Network-on-Chips

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20110191646A1
SERIAL NO

12922948

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.

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Patent Owner(s)

  • OHIO UNIVERSITY;THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA;ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA, ACTING FOR AND;ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA, ACTING FOR AND ON BEHALF OF THE UNIVERSITY OF ARIZONA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kodi, Avinash K Athens, US 3 5
Louri, Ahmed Tucson, US 11 29
Roveda, Janet Meiling Wang Tucson, US 3 5
Sarathy, Ashwini Hillsboro, US 3 5

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