SEMICONDUCTOR DEVICE FABRICATION METHOD

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United States of America Patent

APP PUB NO 20110207290A1
SERIAL NO

13017507

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films.

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Patent Owner(s)

Patent OwnerAddress
OKI SEMICONDUCTOR CO LTD550-1 HIGASHIASAKAWA-CHO HACHIOJI-SHI TOKYO 193-8550

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nishimura, Hidetomo Miyagi, JP 5 13

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