SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATION

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United States of America Patent

SERIAL NO

13132100

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Abstract

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In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INC4453 NORTH FIRST STREET SUITE 100 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Palmer, Robert E Carrboro, US 50 996
Poulton, John W Chapel Hill, US 118 2304

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