Methods of forming p-channel field effect transistors having SiGe source/drain regions

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United States of America Patent

PATENT NO 8198194
APP PUB NO 20110237039A1
SERIAL NO

12729486

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Abstract

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Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

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Patent Owner(s)

  • CHARTERED SEMICONDUCTOR MANUFACTURING LTD.;INFINEON TECHNOLOGIES AG;INTERNATIONAL BUSINESS MACHINES CORPORATION;SAMSUNG ELECTRONICS CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dyer, Thomas W Pleasant Valley, US 106 2537
Han, Jin-Ping Fishkill, US 53 600
Lai, Chung Woh Singapore, SG 30 238
Lee, Hyung-rae Seoul, KR 13 113
Utomo, Henry K Newburgh, US 71 1502
Yang, Jong Ho Gyeonggi-do, KR 15 1033

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