SEMICONDUCTOR LAMINATION PACKAGE AND METHOD OF PRODUCING SEMICONDUCTOR LAMINATION PACKAGE
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United States of America Patent
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N/A
Issued Date -
Oct 6, 2011
app pub date -
Mar 29, 2011
filing date -
Mar 30, 2010
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A semiconductor lamination package includes a first package with a first semiconductor chip mounted thereon and a second package with a second semiconductor chip mounted thereon. The first package includes first mounting pads disposed on a bottom surface thereof for transmitting an input/output signal externally from the first semiconductor IC chip. The second package is laminated on the bottom surface of the first package. The second package includes a package substrate having first bonding pads disposed on one surface thereof and second mounting pads disposed on the other surface and electrically connected to the first bonding pads; a first wiring portion for electrically connecting the first bonding pads to a chip pad of the second semiconductor chip; and a package bonding substrate having connecting pads disposed on an upper surface of the second package and a wiring path for electrically connecting the connecting pads and the chip pad.
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