Router design for 3D network-on-chip
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United States of America Patent
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Mar 5, 2013
Grant Date -
Oct 6, 2011
app pub date -
Mar 31, 2010
filing date -
Mar 31, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
A network-on-chip router which includes an input buffer, an input controller connected to said input buffer, an arbiter connected to said input controller, a crossbar connected to said arbiter and said input buffer, and an output buffer connected to said crossbar. The network-on-chip router minimizes propagation time of data through the router by ensuring that the propagation delay of data through an input buffer is less than the combined propagation delay of data through an input controller and arbiter.
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