Using edges of self-assembled monolayers to form narrow features
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United States of America Patent
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Issued Date -
Dec 1, 2011
app pub date -
May 21, 2003
filing date -
May 21, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention provides a method for manufacturing a structure over a semiconductor substrate. To form a trench, a patterned layer is formed on a portion of a substrate such that the patterned layer forms a target area located adjacent an edge of the patterned layer. A self-assembled monolayer (SAM) is coupled to the substrate up to the patterned layer, but excluded from the patterned layer. The substrate is then removed within the target area. A wire is formed in a similar fashion except that the first SAM is exchanged with a second SAM in the target area. Then either the substrate outside of the target area is removed, or conductive metal crystals are grown within the target area. Such structures may be advantageously used in the manufacture of a number of active or passive electronic devices, such as a field effect transistor.
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