Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof
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United States of America Patent
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Issued Date -
Dec 8, 2011
app pub date -
Jun 1, 2011
filing date -
Jun 8, 2010
priority date (Note) -
Abandoned
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Abstract
A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The memory elements of the multiple layers are formed simultaneously in an orientation parallel to the substrate thereby reducing processing cost. In another aspect, a diode is formed in series with each memory element to reduce current leakage. The diode is incorporated within a pillar line acting as a bit line without taking up additional space.
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