Importance

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Abstract

A stacked chip package structure includes: a first chip and a second chip stacked on a substrate; a first electrical connection structure electrically connecting the substrate and the first chip; and a second electrical connection structure electrically connecting the second chip and the first chip, wherein the second electrical connection structure, disposed on a third chip, includes an adhesive layer encapsulating a second solder ball structure on the second chip and a first solder ball structure on the first chip; and a plurality of conductive wires disposed in the adhesive layer for conducting the second solder ball structure and the first solder ball structure. A fabrication method for the stacked chip package structure is also disclosed. Forming conductive wires in the adhesive layer electrically connecting the upper and lower chips may improve potential problems caused when using wire bonding technology for the upper chip during stacking of the multilayer chips.

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First Claim