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Abstract

A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be associated with a different bank set in the memory IC. These bank sets may be micro-threaded so that each bank set is independently addressable and can concurrently perform operations associated with independent commands, including simultaneous column read/write. Furthermore, temporally interleaved data-mask information for the write-data sequences may be communicated from the memory controller to the memory IC via a data-mask link, so that alternate bits in the interleaved data-mask information may correspond to different write sequences.

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First Claim