Analog-to-digital converter timing circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 10, 2012
Grant Date -
Dec 22, 2011
app pub date -
Dec 10, 2008
filing date -
Dec 13, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An analog-to-digital converter timing circuit disclosed herein uses a clock generation circuit that makes the analog-to-digital converter insensitive to input clock duty cycle. Minimum clock jitter is added to the clock signal while propagating through the disclosed circuit. A method and system are also disclosed to clock an interleaved pipelined ADC such that the operation is insensitive to input clock duty cycle and such that the clock jitter on the sampling clock edges is minimized.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully