Semiconductor package structure and forming method thereof
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United States of America Patent
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Issued Date -
Jan 26, 2012
app pub date -
Sep 23, 2010
filing date -
Jul 23, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention provides a semiconductor package structure, which includes a substrate having a top surface and a back surface, a plurality of first connecting points on the top surface and a plurality of second connecting points on the back surface; a chip having an active surface and back surface, a plurality of pads on the active surface, and the chip is attached on the top surface of the substrate; a plurality of wires is electrically connected the plurality of pads on the active surface of the chip with the plurality of first connecting points on the top surface of substrate; a first encapsulant is filled to cover portion of the plurality of wires, the chip, and the portion of top surface of the substrate; a second encapsulate is filled to cover the first encapsulant, the plurality of wires and is formed on portion of the top surface of the substrate, in which the Yang's module of the second encapsulant is different with that of the first encapsulant; and a plurality of connecting components is disposed on the back surface of the substrate and is electrically connected the plurality of second connecting points.
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