US Patent Application No: 2012/0039,139

Number of patents in Portfolio can not be more than 2000

Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations

ALSO PUBLISHED AS: 8281055

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Abstract

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Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1314

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shaeffer, Ian San Jose, CA 69 202

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