Method of fabricating semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8748266
APP PUB NO 20120052675A1
SERIAL NO

13291999

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Abstract

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In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATION2-24 TOYOSU 3-CHOME KOUTOU-KU TOKYO 135-0061

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Imai, Yasuo Takasaki, JP 48 432
Kobayashi, Masayoshi Takasaki, JP 123 1688
Kubo, Sakae Takasaki, JP 18 242
Kudo, Satoshi Maebashi, JP 77 782
Nakazawa, Yoshito Takasaki, JP 108 1477
Numazawa, Sumito Takasaki, JP 16 221
Ohnishi, Akihiro Isesaki, JP 20 285
Oishi, Kentaro Takasaki, JP 36 330
Shigematsu, Takashi Takasaki, JP 93 1340
Uesawa, Kozo Sawa-gun, JP 16 221

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