Semiconductor die package including low stress configuration
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United States of America Patent
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Feb 28, 2017
Grant Date -
Apr 5, 2012
app pub date -
Dec 13, 2011
filing date -
Jan 24, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
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