Semiconductor integrated circuit design apparatus and method for analyzing a delay in a semiconductor integrated circuit
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United States of America Patent
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Jun 4, 2013
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Apr 19, 2012
app pub date -
Apr 21, 2010
filing date -
May 20, 2009
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Abstract
A semiconductor integrated circuit design apparatus for analyzing a delay in a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay analysis unit, a noise generation unit, a voltage fluctuation level analysis unit and a timing verification unit. The noise generation unit generates noise information based on a predetermined noise definition and the voltage fluctuation level analysis unit analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the generated noise information. Further, the timing verification unit makes the delay analysis unit analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis.
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