US Patent Application No: 2012/0112,873
Number of patents in Portfolio can not be more than 2000
VIALESS INTEGRATION FOR DUAL THIN FILMS - THIN FILM RESISTOR AND HEATER
ALSO PUBLISHED AS:
8558654
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May 10, 2012
Publication date -
Dec 29, 2011
filing date -
13/340,255
serial no -
Granted
status (Latency Note)
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Abstract
A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.
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First Claim
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International Classification(s)
Cited Art Landscape
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| * 5,635,893 Resistor structure and integrated circuit | 30 | 1995 | |
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| * 8,242,876 Dual thin film precision resistance trimming | 11 | 2009 | |
* Cited By Examiner