Vialess integration for dual thin films—thin film resistor and heater
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United States of America Patent
Stats
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Oct 15, 2013
Grant Date -
May 10, 2012
app pub date -
Dec 29, 2011
filing date -
Sep 17, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.
First Claim
Family
International Classification(s)
Cited Art Landscape
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Patent Citation Ranking
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| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Apr 15, 2025 |
| Fee | Large entity fee | small entity fee | micro entity fee |
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| Surcharge - 3.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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