Selecting programming voltages in response to at least a data latch in communication with a sense amplifier

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8339858
APP PUB NO 20120113722A1
SERIAL NO

13285697

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that is in communication with the sense amplifier.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
MICRON TECHNOLOGY, INC.BOISE, ID19030

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aritome, Seiichi Boise, US 291 6140

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (1)
6975542 NAND flash memory with improved read and verification threshold uniformity 73 2003
 
SANDISK TECHNOLOGIES LLC (3)
7187585 Read operation for non-volatile storage that includes compensation for coupling 118 2005
7206235 Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling 36 2005
7286406 Method for controlled programming of non-volatile memory exhibiting bit line coupling 12 2005
 
MACRONIX INTERNATIONAL CO., LTD. (1)
7072219 Method and apparatus for operating a non-volatile memory array 10 2004
 
MICRON TECHNOLOGY, INC. (8)
* 6654272 Flash cell fuse circuit 27 2001
* 6845029 Flash cell fuse circuit 25 2003
* 7002828 Flash cell fuse circuit 15 2003
6977842 Boosted substrate/tub programming for flash memories 53 2003
6982905 Method and apparatus for reading NAND flash memory array 49 2003
* 7277311 Flash cell fuse circuit 1 2005
* 7400532 Programming method to reduce gate coupling interference for non-volatile memory 67 2006
7660158 Programming method to reduce gate coupling interference for non-volatile memory 80 2008
 
SAMSUNG ELECTRONICS CO., LTD. (1)
7254064 Flash memory device having multi-level cell and reading and programming method thereof 21 2006
 
KABUSHIKI KAISHA TOSHIBA (1)
5528547 Electrically erasable programmable read-only memory with electric field decreasing controller 27 1994
 
ANALOG DEVICES, INC. (1)
2004/0109,361 SOURCE-BIASED MEMORY CELL ARRAY 15 2002
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

  • No Forward Cites to Display

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
7.5 Year Payment $3600.00 $1800.00 $900.00 Jun 25, 2020
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jun 25, 2024
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00