Systems And Methods For Inspecting And Controlling Integrated Circuit Fabrication Using A Calibrated Lithography Simulator

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United States of America Patent

APP PUB NO 20120117520A1
SERIAL NO

13290801

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Abstract

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A system and method for precise control of fine-line photolithography is disclosed. The system includes a wafer inspector that detects and measures edges and contours of patterns as produced on a wafer and a lithography simulator. The method calibrates the lithography simulator using multiple measurements and/or edges of patterns on the wafer. The calibrated lithography simulator is used to simulate processing to permit optimization of processing conditions by iterative adjustment and re-simulation. In embodiments, the process conditions optimized include one or more of dose, placement of edges on masks, and placement, shape, and locations of SRAF/OPC structures on the masks. In embodiments, the method includes using the calibrated lithography simulator to match results of production process equipment to those achieved with standard equipment. In embodiments, process data from multiple process simulations is stored in a single image file. The method concludes with fabrication of wafers using the optimized conditions and masks.

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Patent Owner(s)

Patent OwnerAddress
NGR INC2-6-23 SHIN-YOKOHAMA KOHOKU-KU YOKOHAMA-SHI KANAGAWA 2220033 ?2220033

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ishikawa, Akio Yokohama, JP 60 655
Kitamura, Tadashi Yokohama, JP 30 767

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