Semiconductor device having plural banks

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8630129
APP PUB NO 20120134217A1
SERIAL NO

13304062

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
LONGITUDE SEMICONDUCTOR S.A.R.L.LUXEMBOURG, LU2004

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujisawa, Hiroki Tokyo, JP 154 1293
Motoyama, Yuuji Tokyo, JP 3 6

Cited Art Landscape

Patent Info (Count) # Cites Year
 
QIMONDA AG (1)
* 2010/0070,676 Memory Data Bus Placement and Control 1 2008
 
POLARIS INNOVATIONS LIMITED (2)
* 2002/0174,313 Method of matching different signal propagation times between a controller and at least two processing units, and a computer system 3 2002
* 2011/0205,828 SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACCESS SPEEDS 4 2010
 
LONGITUDE SEMICONDUCTOR S.A.R.L. (2)
7719922 Address counter, semiconductor memory device having the same, and data processing system 6 2008
2009/0010,091 ADDRESS COUNTER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND DATA PROCESSING SYSTEM 1 2008
 
SAMSUNG ELECTRONICS CO., LTD. (1)
* 2002/0149,990 Semiconductor memory device having asymmetric data paths 1 2002
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
L-3 COMMUNICATIONS CORPORATION (1)
* 8885777 Digital signal processing apparatus with a delay memory having a plurality of memory cells and process for using same 0 2012
 
SK HYNIX INC. (1)
* 2014/0055,162 ON-DIE TERMINATION CIRCUIT 3 2012
* Cited By Examiner

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