Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
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United States of America Patent
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Mar 18, 2014
Grant Date -
Jun 21, 2012
app pub date -
Feb 28, 2012
filing date -
Dec 26, 1997
priority date (Note) -
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Abstract
In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
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