Digital modulation jitter compensation for polar transmitter

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United States of America Patent

PATENT NO 9699014
SERIAL NO

13412533

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Abstract

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This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

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Patent Owner(s)

Patent OwnerAddress
INFINEON TECHNOLOGIES AGNEUBIBERG

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kuttner, Franz St. Ulrich, AT 69 482
Schimper, Markus Moosinning, DE 26 257

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