Semiconductor Package with Reduced On-Resistance and Top Metal Spreading Resistance with Application to Power Transistor Packaging
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United States of America Patent
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Issued Date -
Jul 12, 2012
app pub date -
Jul 20, 2011
filing date -
Jan 10, 2011
priority date (Note) -
Abandoned
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Abstract
Some exemplary embodiments of a semiconductor package including a semiconductor device having electrodes on opposite major surfaces connectable to a planar support surface without a bondwire and a control electrode disposed in a corner position for reducing top-metal spreading resistance and device on-resistance have been disclosed. One exemplary structure comprises a semiconductor device having a first major surface including a first electrode and a second major surface including a second electrode and a control electrode, wherein the control electrode is disposed in a corner of the second major surface, and wherein the first electrode, the second electrode, and the control electrode are electrically connectable to a planar support surface without a bondwire. The pads of the device may be arranged in a balanced grid to maintain device stability during integration. A minimum gap distance between die pads allows the placement of vias in the planar support surface.
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