Shared Electrostatic Discharge Protection For Integrated Circuits, Integrated Circuit Assemblies And Methods For Protecting Input/Output Circuits
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United States of America Patent
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Issued Date -
Jul 19, 2012
app pub date -
Jan 19, 2011
filing date -
Jan 19, 2011
priority date (Note) -
Abandoned
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Abstract
A method for protecting input/output (I/O) circuits on an integrated circuit (IC) from electrostatic discharge (ESD) is disclosed. The method includes the steps of providing at least one protective device on a surface of a first semiconductor die and applying a conductive shorting layer over a select region of the surface to electrically couple at least one metallic stud to the at least one protective device. After bonding the IC die to a second IC die and/or testing one or more core circuits, the conductive shorting layer is removed to enable high-speed I/O connections arranged in the select region of the semiconductor die. An IC assembly includes first and second semiconductor dice. One of the dice includes a protective device along a surface. An electrically conductive shorting layer couples the protective device to a conductive element that is further coupled to I/O circuit elements.
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