Bilayer trench first hardmask structure and process for reduced defectivity

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8796150
APP PUB NO 20120187546A1
SERIAL NO

13012166

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Abstract

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A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GLOBALFOUNDRIES INC.SUNNYVALE, CA16267

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akinmade-Yusuff, Hakeem B S Beacon, US 6 7
Choi, Samuel Sung Shik Beacon, US 2 8
Engbrecht, Edward R Poughkeepsie, US 3 43
Fitzsimmons, John A Poughkeepsie, US 104 912

Cited Art Landscape

Patent Info (Count) # Cites Year
 
TESSERA ADVANCED TECHNOLOGIES, INC. (1)
7071054 Methods of fabricating MIM capacitors in semiconductor devices 12 2004
 
IMEC (1)
* 2006/0264,033 Dual damascene patterning method 14 2006
 
LAM RESEARCH CORPORATION (1)
7078350 Methods for the optimization of substrate etching in a plasma processing system 6 2004
 
UNITED MICROELECTRONICS CORP. (2)
2008/0171,433 DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF 10 2007
7704870 Via-first interconnection process using gap-fill during trench formation 1 2008
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (3)
6995085 Underlayer protection for the dual damascene etching 1 2003
2006/0003,576 Dual damascene trench formation to avoid low-K dielectric damage 5 2004
7291553 Method for forming dual damascene with improved etch profiles 4 2005
 
MOSEL VITELIC, INC. (1)
2005/0191,822 Shallow Trench Isolation Method for a Semiconductor Wafer 2 2005
 
RENESAS ELECTRONICS CORPORATION (1)
7485566 Method of manufacturing semiconductor device 2 2006
 
APPLIED MATERIALS, INC. (3)
7226853 Method of forming a dual damascene structure utilizing a three layer hard mask structure 27 2002
* 2003/0119,307 Method of forming a dual damascene structure 65 2002
6853043 Nitrogen-free antireflective coating for use with photolithographic patterning 17 2002
 
GLOBALFOUNDRIES INC. (7)
5686354 Dual damascene with a protective mask for via etching 54 1995
7378738 Method for producing self-aligned mask, articles produced by same and composition for same 6 2003
7393777 Sacrificial metal spacer damascene process 6 2004
7326651 Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material 3 2004
* 2005/0079,701 METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL 4 2004
2009/0200,683 INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME 12 2008
7655547 Metal spacer in single and dual damascene processing 2 2008
 
SAMSUNG ELECTRONICS CO., LTD. (3)
2004/0038,521 Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process 1 2003
7598168 Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer 5 2005
2008/0200,026 Method of forming fine metal patterns for a semiconductor device using a damascene process 11 2007
 
FUJITSU SEMICONDUCTOR LIMITED (2)
2004/0137,711 Method for manufacturing semiconductor device 4 2003
7211519 Method for manufacturing semiconductor device 7 2005
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (3)
6184138 Method to create a controllable and reproducible dual copper damascene structure 70 1999
6252290 Method to form, and structure of, a dual damascene interconnect device 67 1999
7247555 Method to control dual damascene trench etch profile and trench depth uniformity 8 2004
 
TOKYO ELECTRON LIMITED (1)
* 2010/0216,310 Process for etching anti-reflective coating to improve roughness, selectivity and CD shrink 2 2009
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
GLOBALFOUNDRIES INC. (2)
* 9478506 Multilayer pattern transfer for chemical guides 0 2013
* 2014/0252,660 MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES 0 2013
* Cited By Examiner

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