PACKAGING STRUCTURE
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United States of America Patent
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Issued Date -
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app pub date -
Apr 17, 2012
filing date -
May 20, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.
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