Importance

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Abstract

A display panel is disclosed has a plurality of source data lines and at least a first and a second gate scan lines and includes at least a first, a second, a third and a fourth display rows. Gates of a plurality of the first and second driving transistors of the first and the second display rows respectively are commonly coupled to the first gate scan line. First sources/drains of the first and the fourth driving transistors are sequentially coupled to odd columns of the source data lines. First sources/drains of the second and the third driving transistors are sequentially coupled to even columns of the source data lines. Gates of a plurality of the third and fourth driving transistors of the third and the fourth display rows respectively are commonly coupled to the second gate scan line.

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First Claim