Package 3D interconnection and method of making same
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United States of America Patent
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Jun 23, 2015
Grant Date -
Sep 6, 2012
app pub date -
Apr 26, 2012
filing date -
Mar 3, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.
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