SYSTEM AND METHOD FOR VERIFICATION AND VALIDATION OF REDUNDANCY SOFTWARE IN PLC SYSTEMS
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United States of America Patent
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Issued Date -
Sep 27, 2012
app pub date -
Mar 9, 2012
filing date -
Mar 23, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Formal methods are instituted to verify and validate the finite state machine (FSM) of PLC redundancy software. The method and system is implemented through each phase in the lifecycle of the redundancy software; that is, the requirement phase, design phase, implementation phase and, finally, integration phase (including system integration). At each step along the way, the verification and validation process uses tools such as a checklist-based review and inspection, a requirement traceability analysis, formal verification (model checking) and the like to ensure that the created redundancy software is error-free and will perform as intended when implemented in the redundant PLC system.
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