Vertical Memory Devices
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United States of America Patent
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Issued Date -
Oct 11, 2012
app pub date -
Mar 28, 2012
filing date -
Apr 5, 2011
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.
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