Three-dimensional stacked substrate arrangements

United States of America Patent

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Apr 16, 2013
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Nov 8, 2012
app pub date
May 14, 2012
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Jul 2, 2003

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Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

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Patent Owner	Address
INTEL CORPORATION	SANTA CLARA CA

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H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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Inventor Name	Address	# of filed Patents	Total Citations
Chan, Michael Y	Sunnyvale, US	12	277
Harmes, Michael C	North Plains, US	7	74
Kim, Sarah E	Portland, US	55	5383
Kobrinsky, Mauro J	Portland, US	133	1696
List, Scott	Beaverton, US	8	425
Marieb, Thomas	Portland, US	13	297
Morrow, Patrick	Portland, US	238	2967
O'Brien, Kevin P	Portland, US	134	665
Ramanathan, Shriram	Hillsboro, US	73	2588

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Three-dimensional stacked substrate arrangements

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United States of America Patent

13470822

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PATENT NO	8421225
APP PUB NO	20120280387A1
SERIAL NO	13470822
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
April 16, 2013	US,8421225,B2 US8421225B2	GRANTED PATENT AS SECOND PUBLICATION
November 08, 2012	US,20120280387,A1 US20120280387A1	FIRST PUBLISHED PATENT APPLICATION

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13470822

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