Method of manufacturing transparent transistor with multi-layered structures
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United States of America Patent
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Apr 2, 2013
Grant Date -
Dec 13, 2012
app pub date -
Aug 21, 2012
filing date -
Dec 22, 2008
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Abstract
A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.
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