Method for wafer level packaging of electronic devices
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United States of America Patent
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Aug 19, 2014
Grant Date -
Dec 20, 2012
app pub date -
Aug 30, 2012
filing date -
Nov 30, 2007
priority date (Note) -
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Abstract
A method of packaging a semiconductor device that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.
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