ASYNCHRONOUS CLOCK ADAPTER
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United States of America Patent
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Issued Date -
Jan 3, 2013
app pub date -
Jun 29, 2012
filing date -
Jul 1, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An asynchronous clock adapter is disclosed that transmits multiple data elements from a buffer in a source clock domain to a data register in a destination clock domain. The buffer can be selected by a pointer register in the destination clock domain and a round trip timing path exists from the pointer register to the data register. Data elements from the buffer can be sent on interleaved cycles of the destination clock such that each data element can have a delay constraint of more than one clock period.
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