Methods of forming memory arrays and semiconductor constructions
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United States of America Patent
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Sep 10, 2013
Grant Date -
Jan 10, 2013
app pub date -
Sep 12, 2012
filing date -
May 8, 2007
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Abstract
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
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