Semiconductor package and stacked semiconductor package having the same
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United States of America Patent
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Sep 2, 2014
Grant Date -
Jan 31, 2013
app pub date -
Sep 28, 2012
filing date -
Sep 19, 2008
priority date (Note) -
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Abstract
A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.
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