STACKABLE WAFER LEVEL PACKAGES AND RELATED METHODS
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United States of America Patent
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Issued Date -
Feb 14, 2013
app pub date -
Aug 9, 2011
filing date -
Aug 9, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present semiconductor device packages include a die, a redistribution layer and a plurality of conductive pillars electrically connected to the redistribution layer. A molding compound partially encapsulates the die and the pillars. A plurality of interconnect patterns on the molding compound are electrically connected to the pillars. The interconnect patterns provide electrical connections for a second, stacked semiconductor package.
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