Buffered finFET device
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United States of America Patent
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Feb 4, 2014
Grant Date -
Feb 21, 2013
app pub date -
Aug 19, 2011
filing date -
Aug 19, 2011
priority date (Note) -
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Abstract
One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.
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