Layout of memory cells and input/output circuitry in a semiconductor memory device
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United States of America Patent
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Jul 22, 2014
Grant Date -
Feb 21, 2013
app pub date -
Oct 23, 2012
filing date -
Nov 28, 2008
priority date (Note) -
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Abstract
A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.
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