Method and apparatus for automatic relative placement generation for clock trees

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United States of America Patent

PATENT NO 8984467
SERIAL NO

13212061

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Abstract

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Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC675 ALMANOR AVENUE SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arunachalam, Anand Sunnyvale, US 9 203

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