SRAM read-write memory cell having ten transistors
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United States of America Patent
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Oct 21, 2014
Grant Date -
Feb 28, 2013
app pub date -
Feb 14, 2011
filing date -
Feb 15, 2010
priority date (Note) -
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Abstract
A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.
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