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Abstract

A delay circuit includes at least a delay stage. The delay stage includes an inverting receiver, a capacitive element, an output inverter, and a feedback transistor. The inverting receiver includes a resistive element. An input node of the inverting receiver receives an input signal, and the resistive element is coupled to an output node and an internal node of the inverting receiver. A capacitive element is coupled to the output node of the inverting receiver. An input node of the output inverter is coupled to the output node of the inverting receiver, and an output node of the output inverter outputs an output signal of the delay stage. The feedback transistor is coupled between the output node and the input node of output inverter, such that the feedback transistor compensates a delay time of the inverting receiver as at least one of a process, a supply-voltage, and a temperature varies.

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