Variable read latency on a serial memory bus
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United States of America Patent
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May 13, 2014
Grant Date -
Mar 7, 2013
app pub date -
Nov 5, 2012
filing date -
Dec 23, 2009
priority date (Note) -
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Abstract
Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
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