Methods and Circuits for Duty-Cycle Correction
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United States of America Patent
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Issued Date -
Mar 14, 2013
app pub date -
Sep 12, 2012
filing date -
Sep 14, 2011
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Abandoned
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Abstract
A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.
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